1. Field of the Invention
This invention relates to superconductive Josephson junction memory circuits. More particularly, the invention relates to a high density and high performance Josephson junction memory cell for memory arrays or cache memories.
2. Description of the Prior Art
This invention is an improvement of prior art Josephson junction memory cells and memory circuits. One of the first Josephson junction memory cells described in the literature is entitled "A Subnanosecond Josephson Tunneling Memory Cell With Non-Destructive Readout" by Hans H. Zappe published in the IEEE's Journal of Solid-State Circuits, Vol. SC-10, No. 1, February 1975 at pages 12 to 19. This early memory circuit teaches a single memory cell which employs a minimum of two Josephson junction devices in a superconductive interferometer storage loop. The current in the storage loop can be made to circulate either clockwise or counterclockwise to represent either a logic one or logic zero state. A single control line is employed to couple positive or negative signals to the storage loop and to switch one of the two Josephson junction devices into a high voltage state, thus, selecting the direction of flow of the circulating current in the storage loop. This circuit employs asymmetrical threshold characteristic curves for both of the Josephson junction devices with respect to the control current to provide proper selection of the direction of circulating current of the storage loop. This circuit requires that the memory be initialized employing stronger current than the write pulses.
An array memory is described in "Basic Design of a Josephson Technology Cache Memory" by S. M. Faris, et al published in the IBM Journal of Research and Development, Vol. 24, No. 2, March 1980 at pages 143 to 154. This article recognized the problems associated with the aforementioned Zappe memory cell. The article teaches a three Josephson junction superconducting interferometer in one of the branches of a storage loop. The purpose of employing the three Josephson junctions in the interferometer storage loop was to provide a symmetrical threshold characteristic curve which in turn enhances the operating margin of the three Josephson junction devices and dispenses with the requirement of directional control currents for selecting a logical state represented by circulating current in the storage loop. In the S. M. Faris, et al storage cell, a logic one is represented by a circulating current in the storage loop and a logic zero is represented by no circulating current in the storage loop.
While the S. M. Faris, et al article teaches how to eliminate some of the problems associated with the earlier storage cells, this improvement was achieved by employing a larger number of Josephson junction devices in the storage loop, thus, employing more area on an integrated circuit chip to achieve the improvement.
It would be desirable to provide a new and novel Josephson junction memory circuit which would combine all of the features of the prior art memory cells and storage loops and yet employ fewer Josephson junction devices so that higher density integrated circuits could be made. Not only would the density of the storage loops be improved, but the employment of fewer Josephson junction devices for each memory cell increase the yields of useable devices.